1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device including a data output circuit to support a pre-emphasis operation.
2. Description of the Related Art
FIG. 1A is a block diagram illustrating a conventional data output circuit.
Referring to FIG. 1A, the conventional data output circuit includes a pull-up pre-main driver 110, a pull-up main driver 120, a pull-down pre-main driver 130, and a pull-down main driver 140.
The pull-up pre-main driver 110 and the pull-down pre-main driver 130 are configured to invert and drive output data OUT_DATA and to output pull-up drive data PU_PMDATA and pull-down drive data PD_PMDATA, respectively.
The pull-up main driver 120 is configured to drive a data output pad DQ to an external power supply voltage VDD in a period where the pull-up drive data PU_PMDATA is at a logic low level.
The pull-down main driver 140 is configured to drive the data output pad DQ to an external ground voltage VSS in a period where the pull-down drive data PD_PMDATA is at a logic high level.
FIG. 1B is a timing diagram explaining an operation of the conventional data output circuit illustrated in FIG. 1A.
Referring to FIG. 1B, it can be seen that, when the output data OUT_DATA driven to the data output pad DQ maintain the same logic level during two or more data periods, the voltage level of the data output pad DQ rises more than or drops less than a normal level, that is, the voltage level of the data output pad DQ varies.
Specifically, in a period 1 where the output data OUT_DATA driven to the data output pad DQ maintains a logic low level during two data periods, the voltage level of the data output pad DQ drops slightly more than a normal voltage level corresponding to a logic low level.
When the output data OUT_DATA driven to the data output pad DQ changes from a logic low level to a logic high level after the voltage level of the data output pad DQ dropped slightly more than the normal voltage level corresponding to a logic low level, the voltage level of the data output pad DQ becomes slightly lower than the normal voltage level corresponding to a logic high level (2). In FIG. 1B, the period where the data output pad DQ maintains a voltage level which is slightly lower than a normal voltage level corresponding to a logic high level corresponds to only one data period. However, since such a phenomenon repetitively occurs, the voltage level variation of the data output pad DQ inevitably increases.
Then, in a period 3 where the output data OUT_DATA driven to the data output pad DQ maintains a logic high level during three data periods, the voltage level of the data output pad DQ rises slightly more than the normal voltage level corresponding to a logic high level.
When the output data OUT_DATA driven to the data output pad DQ changes from a logic high level to a logic low level after the voltage level of the data output pad DQ rose slightly more than the normal voltage level corresponding to a logic high level, the voltage level of the data output pad DQ becomes slightly higher than the normal voltage level corresponding to a logic low level (4). In FIG. 1B, the period where the data output pad DQ maintains a voltage level which is slightly higher than the normal voltage level corresponding to a logic low level corresponds to only one data period. However, since such a phenomenon repetitively occurs, the voltage level variation of the data output pad DQ inevitably increases.
In the above-described data output circuit, the voltage level of the data output pad DQ may become higher or lower than an expected level, according to the logic level of the output data OUT_DATA. Accordingly, jitter of the data OUT_DATA outputted through the data output pad DQ may increase, that is, inter symbol interference (ISI) may become serious. Furthermore, due to such a problem, a data valued window (tDV) of the data OUT_DATA outputted through the data output pad DQ may not be sufficiently secured. In this case, a data output error may occur.